资源列表
滤波器实验报告
- 设计一个 1MHz 的 FIR 低通滤波器。 要求： ① 时钟信号频率 16MHz; ② 输入信号位宽 8bits，符号速率 16MHz ③ 要求在 Matlab 软件中进行 FIR 滤波器浮点和定点仿真，并确定 FIR 滤波器抽头系数 ④ 写出测试仿真程序。(Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width
hdmi
- HDMI协议的Verilog实现，通过对RGB三个通道分别进行TMDS编码完成，纯原创代码(Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code)
uart
- 电脑端发送数据与FPGA接收数据程序，uart模块，以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)
axi lite 接口
- 该文件完成了简单的axi lite 接口协议 Verilog 语言编程。欢迎交流讨论
xilinx_usb_drivers_win10_x64
- win10的xilinx usb驱动，较新版本(Xilinx USB driver for win10, newer version)
multi
- 基于Verilog HDL 的乘法器，可以实现一些功能的计算(Multiplier based on Verilog HDL)
SystemC片上系统设计
- SystemC片上系统设计, 大学课本, 仅供学习参考(SystemC system-on-chip design, university textbook, for reference only)
oled
- 驱动0.96寸的oled显示数字和字母，(Drive 0.96 inch OLED to display numbers and letters.)
adc_cfg
- adc器件ads62p49配置代码，已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)
adc_data_receive
- adc器件ads62p49模数转换代码，已在工程中验证可用(ADC device ads62p49 analog-to-digital conversion code has been validated in Engineering)
RS232
- 串口收发代码，可设置速率，工程中已验证可用(Serial transceiver code, can set the rate, the project has been verified to be available)
UVM验证平台搭建
- 搭建uvm验证平台,通用验证平台结构和搭建流程介绍(How to build a common UVM verification platform?An easy and useful method is instroduced here.)