资源列表
ASKMod
- ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。-ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.
E4_4_IIR4Functions
- 用verilog语言实现的一个IIR滤波器，因为现在的ise等工具中没有包含相关的ip核，所以需要手动设计。 -With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
digital_clock
- 基于vivado的FPGA数字闹钟的程序，verilog语言编写-Vivado based on the FPGA digital alarm clock procedures, verilog language
project_fir_test
- 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
candy_machine
- Verilog Code for Candy Machine State Machine
universal_prescalar
- Verilog Code for universal prescalar
priority_decoder
- Verilog Code for priority decoder
seven_segment
- Verilog Code for 7Segment Decoder
VHDL--PCF8563T
- I2C实践，-PCF8563T实时时钟vhdl语言-I2C practice,-PCF8563T real-time clock vhdl language
VHDLfmq
- FPGA驱动蜂鸣器，vhdl语言，蜂鸣器奏乐-FPGA, vhdl language, buzzer music
Verilog-fmq
- FPGA驱动蜂鸣器，Verilog语言，蜂鸣器奏乐-FPGA driver buzzer, Verilog language, buzzer music
Multiplier
- 复用全加器来实现乘法器, 通过从右到左互为输入输出，实现低位计算。最左向高位输出。具体要求请参见附带的PDF。-Multiplexing a multiplier to achieve full adder, input and output by each other right to left, the least significant bits is calculated. Most left output to high. Specific requirements Refer to