资源列表
CST_-_Smajlici
- VHDL school work. Display four smiles on 8x8 matrix display. It use four button to :--VHDL school work. Display four smiles on 8x8 matrix display. It use four button to :-))
alphabeta_transform
- alpha beta transformation, for FPGA synthesis and implementation
myAdc9248
- CycloneIV控制采样芯片AD9248-20MHz，VHDL语言-CycloneIV control sampling chip AD9248-20MHz, VHDL language
ROM
- FPGArom的IP核使用及仿真,Verilog语言，非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
Filter_Convolution_Example
- Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx
synd
- Syndrome calculator basic unit for reed solomon decoder in verilog language
behavioral-hmwk5
- Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.
code
- Design the logic required for a “Dancing Light” system including 5 lights which are turned on repeatedly
code-hmwk7
- Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram
hmwk3try.vhd
- Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined variable
verilog_experiment
- 关于verilog的数码管显示，简单的输入输出，流水灯-about verilog test in and out ,about light on and off
ad706_verilog
- AD706在Sparten6使用的FPGA代码，测试通过-AD706 FPGA Code In Sparten6