资源列表
setmin_sec
- 用QuartusII13.0软件，DE1开发板实现的时钟程序，可设定的时间-With QuartusII13.0 software, DE1 development board to achieve the clock procedures can be set up time
FPGA_Projects_100
- FPGA_Projects_100，例程100例经典程序-FPGA examples
DDS
- 基于FPGA，Verilog语言编写的DDS信号发生器，可生成方波、正玄波，三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
FINAL_CODE_CAM
- this is a VHDL code for content address memory
ex_2
- FPGA 代码,可以作为练习VIVADO的使用于学习- CS_r[0] < CS CS_r[1] < CS_r[0] wrreq_r[0] < wrreq wrreq_r[1] < wrreq_r[0] READ_sig_old[0] < READ_sig READ_sig_old[1] < READ_sig_ol
ADS2807_Ctrl
- ADS2807控制,模块功能：取回控制字，控制AD采样速率和AD的地址发生器-ADS2807 control, module function: retrieve control word, control AD sampling rate and AD address
sgmii
- 这是有关V5中有关SGMII的开发例程，对于学习SGMII的同学会有帮助-This is the development of relevant V5 relevant SGMII routines, are helpful for learning SGMII homecoming
xapp897
- Video streaming example VHDL
DE2_115_ControlPanel_V2.2.0
- This file may be support learn VHDL code
25mto8k
- fpga编码，vhdl，将25m信号分频为8k信号，已仿真验证-fpga 25m to 8k
CNT12
- 通过一个简单完整而典型的12进制计数器的VHDL设计实例，来使大家初步了解用VHDL表达以及由此而引出的VHDL语言现象和语句规则。 让大家能够迅速的从整体上把握VHDL程序的基本结构和设计特点，达到快速入门的目的。 -Through a simple and complete and typical 12-band counter VHDL design examples, to make preliminary understanding of VHDL expression and the
fenpin5
- 五分频器的VHDL语言设计，改变相关参数，可得到其他分频器，便于学习VHDL语言-Five frequency divider VHDL language design, change the relevant parameters, you can get other dividers, easy to learn VHDL language