资源列表
VerilogBasicICDesign
- Verilog基本电路设计,包括时钟域同步、无缝切换、 异步FIFO、去抖滤波-Verilog basic circuit design, including clock domain synchronization, seamless switching, asynchronous FIFO, debounce filter
Based-SystemVerilog-ofAMBA-Bus
- 本论文是基于systemverilog的AMBA总线的实现，是学习systemverilog的一份好资料-This paper is based on systemverilog AMBA bus implementation, is to learn systemverilog a good information
Writing-TBusing-SystemVerilog
- 本书是关于如何用systemverilog写测试台程序的，对于搞验证和测试的人绝对有用-This book is about how to use the systemverilog write test bench program, for those who engage in verification and testing is absolutely useful
conv
- Conv Encoder for VHDL Vivado
SPI_TEST
- verilog SPI 读写时序，测试验证OK.-SPI Verilog Code, Master and Slaver.
Projekt7_GenericMultiplexer
- Simple Generic Multiplexer in VHDL
eight_bit_spi
- Interface for SPI bus words 8bits with availability to loop the exchange
DSP-IN-FPGA
- 何宾所著的关于FPGA用于实现DSP的设计方法与原理，非常详细，对初学者帮助很大 -He Bin on the FPGA used to achieve the DSP design methods and principles, very detailed, great help for beginners
detector_vhdl_sources
- this a vhdl code for the generation of an hyperchaotique systeme lorenz systeme-this is a vhdl code for the generation of an hyperchaotique systeme lorenz systeme
StepperMotor_control_follow
- 本源码是基于FPGA来控制步进电机运行上位机发出的精确步数，并能够实时跟踪步进电机行进的位置，通过UART接口与上位机进行串口通信。-The source code is based on FPGA to control the stepper motor running the host computer to send the exact number of steps, and can track the location of the stepper motor in real time
LED
- LED显示程序，FPGA实现流水灯的显示效果。是入门的好方法。-LED Display.
Adder
- 采用HDL语言实现加法操作，可以作为入门的实验例程。-the adder is design by HDL.