资源列表
PC_FPGA_Communication
- 本软件利用串口实现了电脑和FPGA的通讯。采用vhdl。就是为了FPGA开发的基础软件。-This software uses serial port to realize the communication between computer and FPGA. Using vhdl. this is the basic software to develop the FPGA.
board
- 4位led灯以二进制从0000变化到1111，再从1111变化到0000，外加温度检测-4 led lights change 0000 to 1111 in binary, then change 1111 to 0000, plus temperature measurement
pluse_count
- 以利用FPGA系统时钟分频对定时器进行配置和定时操作。-To take advantage of the FPGA system clock frequency division for timer configuration and operation regularly
freq_100M
- 在FPGA平台上，verilog,频率测量，已调试，可在quartus上打开。-On the FPGA platform, verilog, frequency measurement, debugged, can be opened on quartus.
m-Sequence
- FPGA,verilog,输出M序列，已调试成功，可直接在Quartus上打开。-FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
phase_move
- FPGA平台，ve已调试，verilog语言，实现对波形的移向，模块。-FPGA platform, ve has been debugged, verilog language, to achieve the shift to the waveform, the module.
DDR_TEST
- 基于xc65slx16的ise 14.7 DDR3测试模版，经过验证，可供fpga开发参考学习，也可作为开发模版。-Based on xc65slx16 ise 14.7 DDR3 test template, validated and can be used for reference in the fpga development study, also can be used as a template development.
watch_dog
- 基于EPM1270F256实现的4路看门狗控制逻辑，实现了滤波、延时、复位功能。-Based on EPM1270F256 4 road guard dog control logic, to realize the function of filtering, time delay and reset.
stm32-and-fpga-communication-by-spi
- 该实验完成的功能是STM32与FPGA通信-The function of the experiment is STM32 and FPGA communication
ceshi
- 数字可调正弦波发生器，通过按键可调节频率，10hz到10khz-Digitally tunable sine wave generator, the frequency can be adjusted by buttons, 10hz to 10khz
Error-generation
- 误差产生模块：通过给定值与反馈值做差，产生一个带正负的误差值-Error value by a given value and the feedback value make the difference, resulting in a band of plus or minus: error generating module
Register.vhd
- This file is an asynchronous vhdl Register. It registers the input vector into the output vector when the Enable variable is high.