资源列表
sine_package
- ve verilog va tai lieu
mipsx2
- 基于FPGA的SOC设计与功能测试，利用mips指令集编写的soc片上系统，以及功能验证- SOC design and FPGA-based functional test, use mips instruction set written soc system on a chip, and functional verification
151019_halfadder
- 此程序是FPGA 中用VHDL语言来实现半加器的功能，对于初学者很有参考价值。-This program is FPGA using VHDL language to achieve a half-adder function, a good reference for beginners.
vga
- This VHDL sample demonstrates how to generate a VGA signal to make it possible to connect an FPGA to a monitor. Written for Mimas v2, but probably easily adapted to any other board with a VGA connector on it (that can also be done by manually connect
clock_monitor
- 时钟监测模块，在系统运行过程中，时刻保持对时钟频率的检测-Clock detection module, the system is running, keep the clock frequency detection
inout
- 用于RAM的测试文件，以及testbench-some RAM testingfiles，and its testbench
FPGA_PWM
- 该代码的功能是在FPGA上实现PWM的功能，可以实现矩形波的占空比与频率可调。-The code function is to achieve PWM functions on FPGA, the duty cycle can be achieved with the adjustable frequency rectangular wave.
SOS
- 使用matlab生成SOS滤波器，应用于FPGA的一个小型系统，有一定的参考价值-Using MATLAB to generate SOS filter, applied to a small system of FPGA, there is a certain reference value
ahb_verilog_design
- 代码为ahb interface ，用verilog编写的,包括仿真和综合。-Code for the interface AHB, written in Verilog, including simulation and synthesis.
caacc
- cavcl entorpy coding
Soc_Audio_v5
- DE1 audio soc,xue xi audio process by Altera soc FPGA-DE1 audio soc
code
- 基本元器件代码包括iv nd2 alu acc fa lfsr mux21 等-The basic components of the code include iv nd2 alu acc fa lfsr mux21 etc.