资源列表
adc0809_state
- 利用FPGA驱动DAC0832进行数据采样-Use FPGA drives DAC0832 sampling data
clk_even
- 利用FPGA编写的通用的偶分频，适合初学者使用-Even general division
yima
- 利用VHDL语言编写的译码程序，使用一位数码管进行显示-Using VHDL language decoding program that uses a digital display using VHDL language decoding program that uses a digital tube display
quanjia
- 通过VHDL语言编写的一位全加器程序，该程序是经过元件例化的方式实现-VHDL language through a full adder program, which is the result of component instantiation way to achieve
0~99
- 通过VHDL语言编写的计数器，可以从0开始计数当计到99时再从0开始计数-Counter by VHDL language, you can start counting when the count 0 to 99 and then starts counting 0
RISC_cpu
- 一款8位的RISC-cpu 源码可在modelsim仿真出波形-An 8-bit RISC-cpu source code in modelsim simulation waveforms
ug195
- 这个文档是关于xilinx virtex-5 FPGA板的封装和管脚定义文件，对于使用v5 有很大的帮助-This document is package and pin definitions files about xilinx virtex-5 FPGA board for use v5 great help
ps2
- 这是采用了verilog 语言编写的ps2，也就是键盘和FPGA交互的端口协议，适用于virtex5-This is used ps2 verilog language, which is the keyboard port protocol and interactive FPGA for virtex5
ps2_agreement
- 这是关于键盘和FPGA接口的协议的解读，中英文都有，非常详细，适合要写ps2接口的人-This is the interpretation of the Agreement on the keyboard and FPGA interfaces, the English have, in great detail, for people to write ps2 interface
UART
- verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventi
urat
- rs232的verilog的代码，code is based on verilog language, it is practical, we hope to help
prj_button_anti_shake
- 按键消抖的fpga程序，code is based on verilog language, it is practical, we hope to help