资源列表
tlv1544
- TLV1544的采集程序，使用verilog语言编写，感觉很实用，希望对大家有用-TLV1544 collection procedures, using verilog language, feel useful, hope to adopt
Random-sequence-of-test
- 随机序列的测试源码，使用verilog编写，感觉很有用，希望大家喜欢-Random sequence of test source, the use verilog to write, feel useful, I hope you like
IIC
- Verilog IIC程序，RAM接口，方便调试，一主多从-Verilog IIC program, RAM interface, easy to debug, and more a master
iic_src
- 标准I2C总线时序实现，可以用来初始化I2C设备。-Standard I2C bus timing implementation, can be used to initialize the I2C device。
uartsample
- Xilinx EDK开发 通过FPGA实现UART通信-EDK Xilinx development through FPGA to achieve UART communication
lab3_1
- VHDL利用四位拨盘输入数据，输入两个数，显示于数码管，另两个数码管显示其取反，四个数字再留个数码管上以一秒为周期左移-VHDL use four dial input data, input two numbers displayed on the digital control, the other two digital display its negation, then leave a four-digit digital tube left at one-second cycle
lab4_1
- 时钟同步状态机模块化模板，点击转换信号则转换·至下一状态，设置有按键消颤-Clock synchronization state machine Modular template
lab4_2
- 脉冲宽度测量，按下按键开始脉冲宽度的测量，并设计有复位溢出信号，采用状态机模块化设计方法-Pulse width measurement, press the button to start measuring the pulse width, and the design of the overflow reset signal, using the state machine Modular Design
lab3
- 数码管扫描电路，通过扫描数码管实现多个数码管同时显像功能-Digital scanning circuit, through digital scanning of multiple simultaneous digital imaging capabilities
lab3_2
- 加/减可调十六位计数器，可以清零，代码清晰-Plus/minus sixteen adjustable counter can be cleared, the code clear
Reed-Solomon-RS-ENCODE-DECODE
- 支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码-This program is an encoder/decoder for Reed-Solomon codes.
PWM-Smart_CAR_Project
- FPGA循迹小车，可自回归，可进行PWM互补调速-FPGA car tracking, self-regression, can be complementary PWM Speed