资源列表
liushui
- 本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写-This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
fenpin
- 输出比设定的时钟频率小8倍的时钟，实现分频功能，可用于芯片控制。-Output than the set of 8 times the clock frequency of the clock, to achieve frequency division function, can be used for chip control.
ad-kongzhi
- 主要用于ad的控制，包括时钟的设置和输出地址的控制。-Mainly used for the control of AD, including the clock settings and the output address of the control.
bixiang
- 程序的主要功能是实现两个波形的相位比较，并把输方波。-The main function of the program is to achieve the phase comparison of the two waveforms, and the transmission of the square wave.
hecheng
- 程序实现利用与算法将两个防波信号合成为一个方波输出。-The program and algorithm two wave signal synthesis is a square wave output.
FIFO
- FPGA TI DSP的EMIF接口的地址总线问题-FPGA FIFO
sony_ccd
- SONY CCD DIRIVER，VERILOG
qudong
- 实现驱动红外探测器前端图像采集功能，实现红外热成像镜头的前端采集。-Infrared detector drive to achieve front-end image acquisition, to achieve front-end collection of infrared thermal imaging lens.
fifo
- 使用Verilog实现异步fifo的功能-Use Verilog implementation of asynchronous fifo functionality
FIFO
- 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
demo8-ps2_1_vhdl
- ep1c3实现ps2 Assembler Status Successful - Fri Aug 27 17:48:36 2010 Revision Name ps2_1 Top-level Entity Name ps2_1 Family Cyclone Device EP1C3T144C8-ep1c3 realize ps2,ep1c3 realize ps2,ep1c3 realize ps2
EP1C3-uart_1_verilog
- EP1C3-uart_1_verilog,程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。 串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步.-EP1C3-uart 1 verilog, implements a program