资源列表
divider
- 使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50
shiyan
- 使用FPGA设计的一种跑表，但只是用来实验上的仿真-FPGA design using a stopwatch, but only for simulation on
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
music.tar
- Verilog example of a program that plays some tones when connected to a speaker. Implemmented in FPGA Nexys3
displayCounter2.tar
- Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3-Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Imple
inputPinsTest.tar
- Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific time. Implemmented in FPGA Nexys3-Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific
hcsr04.tar
- Verilog program of the interface between a FPGA and the HCSR04 arduino sensor displaying the distance measured in the 7 segment display. Implemmented in FPGA Nexys3
LCD.tar
- C program of interface with a LCD display using an embedded processor (LatticeMico32) and a Nexys3 FPGA
UsbFPGAdemo
- FPGA底层的USB接口芯片的驱动，用于向上位机传送数据。-Driving USB interface chip FPGA bottom, used to transmit data to the host computer.
FPGA
- 常用的FPGA开发板的资料，方便大家查阅。-PGA development board used to facilitate access to information.
submit
- 用VHDL实现的双人飞机大战。支持PS/2和蜂鸣器。 需要两个CPLD核心协同完成。 含最终效果视频-Multiplayer air fight implemented in VHDL. PS/2 and beeper supported. Two CPLD cores are required to run this demo. Final video includes.
FIFO
- 利用verilog写的异步FIFO的一种写法-Using a written verilog write asynchronous FIFO