资源列表
7 Segment Interfacing
- This source is used for control 7 segments on FPGA board. It is written by VHDL
LCD16x2 Interfacing
- This source VHDL code is used for control LCD16x2 on FPGA
Shift data register
- This is an easy method to register data for FPGA. It is written by VHDL
sequence-detector
- 3比特的任意二值序列检测器，Quartus 10.0+modelsim 6.5SE联仿真报告形式-3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE，report forms
Programmable-filter-design
- 程控滤波器设计，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Programmable filter design,simulation with Quartus 10.0+ modelsim 6.5SE ， reports
Digital-frequency-meter
- 数字频率计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Digital frequency meter,simulation with Quartus 10.0+ modelsim 6.5SE ，reports。
display-circuit
- 计数显示电路 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Counter display circuit,simulation with Quartus 10.0+ modelsim 6.5SE， reports
detector-(1110010)
- 序列检测器（1110010）设计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE ， reports
VHDL-taxi
- 出租车计价器VHDL程序，有备注，适合初学者。-Taximeter VHDL procedures, suitable for beginners.
sencond_counter
- 在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
cnt
- 在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表-In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch
johnson
- 此代码实现约翰逊计数器，内容不多，注释详尽，供初学者使用。-Johnson counts