资源列表
clock
- 多功能数字钟，具有调时校时，整点报时，闹铃及其设定等功能，可直接下载到DE0开发板上-verilog clock
yz
- LCD字符控制显示器设计，显示学号和姓名-Character LCD control display design, student number and name display
top_FFT
- 128k点流水FFT算法的IP核设计，顶层文件，一共13级流水-128k-point FFT algorithm running water IP core design, top-level file, a total of 13 water
butterfly
- FFT模块里的蝶形运算单元，需要用到加法器，减法器，二选一选择器-FFT module of butterflies, need to use an adder, a subtracter, a second election selector
complexMul
- 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
complexadder
- 32位复数加法器，利用ISE里的float IP核-32 complex adder, using the ISE in the float IP core
acc
- This code has function to accumulate
rrc
- This code implement rrc filter
addsub
- This code implement add or sub between 2 number
adder
- This code implement add between 2 number
cordic_base_j
- This code implement a interation in cordic pipelline
grantyz
- 4倍频鉴相功能模块，利用Verilog hdl语言编写的-4x phase function module using Verilog hdl language