资源列表
mux2_1
- 利用QuartusⅡ完成2选1多路选择器的文本编辑输入和仿真测试等步骤，给出仿真波形。-Use QuartusⅡ completed 2-to-1 multiplexer input text editing and simulation testing and other steps, given the simulation waveform.
cic-dicemator
- 该文件包含数字抽取滤波器cic的verilog代码，经测试可用，且简介，消耗硬件资源较少。-This file contains digital sampling filter cic verilog code, after testing is available, and the introduction, less consumption of hardware resources.
timing_controller
- 本程序为船舶导航雷达时序控制模块的整个系统，包含QPF工程。-The program for the entire ship navigation radar system timing control module contains the QPF project.
antenna_position
- 本程序为船舶导航雷达天线方位部分的verilog程序，包含QPF工程。-This procedure for the marine navigation radar antenna part of the Verilog program, including QPF works.
pwm_8.7
- 基于verilog产生多路PWM波形。频率、脉宽可调。带有延时-Based verilog generate multiple PWM waveform.
part1
- LAB 1 - Part 1 DE0 VHDL Tutorial
uart
- 通过CPLD，可以进行和电脑的串口通讯。-By CPLD, and computers can be serial communication.
paralleladder
- This a verilog source code for parallel adder-This is a verilog source code for parallel adder
barrelshifter
- Here is barrel shifter source code with verilog language
Counter1s
- counter number one to nine after 1s-counter number one to nine after 1s
FSM
- lap trinh FSM may trang thai
Decoder
- decoder 3 to 8 verilog