资源列表
cell
- codes for DP ram synthesizable
csa_32
- The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.-The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.
DE2_70_VGA_pattern_gen
- 基于DE2-70的VGA彩条产生程序，适合初学者理解VGA的工作原理-VGA pattern generate in DE2-70
Introduction-to-verillog_good-document
- Introduction to verillog_good document
PWM
- System Verilog语言,功能为实现PWM波形-System Verilog
cube_root
- cube_root使用Verilog语言使用开立方根的算法-cube root
SoCKIT_Materials_14.0
- SocKit FPGA with ARM core -SocKit FPGA with ARM core
SystemC
- System C FPGA仿真软件,与SystemVerilog配合-System C for FPGA
noc_router
- Network on chip router code part1
adc0809
- 1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。-1, with the state machine design A/
decoder
- 学习使用结构描述方法（层次设计），设计4位二进制计数器7段数码显示译码器；学习和掌握模块例化语句应用。-Learn to use the structure described methods (hierarchical design), design 4 binary counter 7-segment display decoder learn and master module instantiation statement applications.
jc1101
- 用状态机实现序列检测器的设计，了解有限状态机的设计与应用。-With a state machine sequence detector design, understand the design and application of finite state machines.