资源列表
edasingene
- 基于FPGA的正弦信号发生器的设计，用verilog语言实现，可调整频率和周期。-FPGA design based on sinusoidal signal generator with verilog language, adjust the frequency and period.
freq
- 基于FPGA的频率计，用verilog语言实现，在标准时钟周期内进行计数，得到信号的频率。-FPGA-based frequency meter, using verilog language, the standard clock counted to obtain the frequency of the signal.
local-bus
- 基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。-FPGA-based local bus interface. Based fifo contains two programs and the general register.
dds
- 这是自己写的dds源码，利用查找表方法，亲测可用。-It is written in their own dds source, using a lookup table method, pro-test available.
Booth2-multiplier
- 一个18bit乘以18bit的Booth2编码的乘法器，已验证通过-A 18bit*18bit booth2 mutiplixer
PipeLine-GCD-DSP
- 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.
systolic_mul_D8_M193
- 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
LCD_Driver_better
- this a characteristic 16x2 LCD Driver by VHDL-this is a characteristic 16x2 LCD Driver by VHDL
plj
- 多功能频率计，可以测量10HZ到10MHZ的频率脉冲，精度为1赫兹，另外有计数器功能-Multifunctional frequency meter, you can measure the frequency of the pulse 10HZ to 10MHZ, and an accuracy of 1 Hz, and another counter function
module-display
- 数码管显示1234，通过调整开关决定数码管显示顺序为1234或4321.-Digital display 1234, by adjusting the switch determines the order of the digital display 1234 or 4321.
Exemple_1_Clock_24
- vhdl code for 24 clok with some options hope u will like it vhdl code for 24 clok with some options hope u will like it vhdl code for 24 clok with some options hope u will like it -vhdl code for 24 clok with some options hope u will like it
Exemple_2_VGA
- my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga-my vhdl code to intrface with a vga my vhdl code to intrface with a vg