资源列表
adc_30hz
- VHDL内部RAM+1KHZ+480点压缩算法+找最大值-VHDL internal RAM+1 KHZ+480 points to find the maximum compression algorithm+
LCD_Driver
- VHDL源码 控制液晶的 希望对大家有用-VHDl
DesignAndTestifyVerilogHDL
- 《设计与验证VerilogHDL》书中程序-design and testify VerilogHDL
code
- these are some of the codes for vhdl
key44
- 4*4按键扫描VHDL程序 在开发板上调试成功,放心使用 -4* 4 keypad scanning process in the development of on-board VHDL debugging success, rest assured that the use of
mc8051_design
- MC8051 core , VHDL , Oregano Systems
CRC_Generator
- This a binary encoded on the check, by check, to verify whether the correct transmission-This is a binary encoded on the check, by check, to verify whether the correct transmission
quartus
- des algorithm send rx from serial port
7
- vhdl七段数码管显示程序，上机实验过，完全正确-Seven-Segment LED display vhdl procedure on the experimental machine, and absolutely correct
1616
- 用vhdl语言描述的16*16点阵显示英文字母-Vhdl language used to describe the 16* 16 dot matrix display alphabetical
fpgafifo
- 基于fpga 实现 fifo 基于FPGA的非对称同步FIFO设计-Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO