资源列表
ZHEJIANG_VHDL
- 浙江大学的VHDL讲义，内容翔实丰富，对想掌握这门语言的同学用处极大，我觉得不错，与大家一同分享。-Materials, Zhejiang University of VHDL, rich informative, and would like to master the language the students use great, I feel good to share with you.
Subroutine
- VHDL常用的22个子程序，适合入门的学习-22 sub-VHDL procedures commonly used for the learning portal
all_packages_20080525.tar
- FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We hav
Test_LED[1]
- 用VHDL实现的一个工程，可以参考来学习FPGA的设计-VHDL achieved with a project, you can reference to learn the design of FPGA
I2c_EEPROM
- I2C VHDL simulation, creates i2c with vhdl for simulation purposes. use it at your own risk.
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_E
- Example VHDL project showing how to use a PWM by CPLD
DE2_TV
- it s so easy and important
TrafficLight
- 用vhdl写的交通灯程序，压缩包内有整个工程文件-With the traffic lights to write vhdl procedure, compressed package files have the whole project
dac
- 用VhdL编程控制芯片实现D/A转换。-VhdL the realization of D/A conversion.
MODELSIM
- Modelsim 经典教程，推荐大家看下-Modelsim Tutorial classic recommend you facie
JTAGFPGAElektor052007
- VHDL universal interface
AnalogandMixedSignalModelingusingVHDL
- The Design Entity is the basic building analog block of a VHDL descr iption.