资源列表
VHDLcode_registr
- VHDL implementation of registors
shuzinaozhong
- 一个数字闹钟的vhdl代码！ 分成几个模块 要通过自顶向下的设计方法来做！-A digital clock vhdl code! Divided into several modules through top-down design method to do!
juzhenjianpan
- 矩阵健盘设计！用了MAXPLUS软件！ 矩阵健盘设计！用了MAXPLUS软件！-juzhenjianpan
I2CVerilog
- VerilogHDL 实现了I2C 文件中包含六个程序 第一个为主程序 其余为子程序 -VerilogHDL achievement of the I2C document contains procedures for the first six the rest of the main program for the subroutine
DigitalWatchVerilog
- 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
10GOpenCore
- 10G Open Cores MAC which is implemented using vhdl langauge
module
- 基于VHDL语言，设计7段LED液晶显示屏，可以下载到相关的xilinx开发板上进行验证-Based on the VHDL language, design 7 LED LCD screen, can be downloaded to the relevant board to verify the development of xilinx
crc
- crc32的 vhdl实现源代码，对crc原理有说明-crc32 to achieve the vhdl source code, has made it clear that the principle of the crc
Verilog_Traffic_light_controller
- Verilog实现的交通灯控制的程序 运行通过无语法错误-Verilog realization of the control of traffic lights run through the non-syntax error
Verilog_Music_liangzhu
- Verilog实现的一首好听的音乐 梁祝，希望对大家有帮助-Verilog realization of a good music Butterfly, I hope all of you help
Verilog_phone_countpay
- VerilogHDL编写的一个电话计费程序 具有一定的代表性-VerilogHDL prepared a telephone billing procedures for a certain degree of representativeness
VHDL
- VHDL语法入门 1.1 VHDL程序构件 1.2 文法规则 1.3 数据对象及类型 1.4 运算符与表达式 1.5 VHDL语句 1.6 进程与子程序 1.7 资源库与程序包-Introduction to VHDL syntax 1.2 Component 1.1 VHDL procedures grammar rules and type of data object 1.3 Operators 1.4 and 1.6 Expression 1.5 VHDL p