资源列表
Virtex-5family
- Virtex™ -5 系列提供 FPGA 市场中最新最强大的功能。Virtex-5 系列采用第二代 ASMBL™ （高级硅片组合模块）列式架构， 包含四种截然不同的平台（子系列），比此前任何 FPGA 系列提供的选择范围都大。每种平台都包含不同的功能配比，以满 足诸多高级逻辑设计的需求。-Virtex ™ -5 family provides the latest FPGA market, the most powerful features. Virtex-5 s
dianzizhong
- 电子时钟程序设计与仿真验证，VHDL语言-Clock Electronics Design and Simulation, VHDL language
diantikongzhi
- 电梯控制器程序设计与仿真验证，VHDL语言-Elevator controller design and simulation verification, VHDL language
unicntr
- 通用寄存器，可以双向计数存储，模式通过三位比特数据进行控制-General registers, can be bi-directional counting storage, mode of data through the three-bit control
verilog_tech
- 本文介绍Verilog HDL语言的发展历史和它的主要能力。并对各种使用进行详细讲解。-This article describes the development of Verilog HDL language and its history, the primary capacity. And explain in detail the various use.
mini-uart
- Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
UART
- 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
Pads-HotKey-Editor
- hardware PCB Pads-HotKey-Editor
UseofFPGA
- 利用FPGA实现的DDS，可输出正弦波，输出频率可调-Use of FPGA implementation of the DDS, sine wave output, output frequency adjustable
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
yinpinxinhaofenxiyi
- 基于vhdl的音频信号分析仪，获电子设计大赛一等奖-VHDL-based audio signal analyzer, an electronic design competition first prize
color_converter.tar
- 非常通用的色度空间变换vhdl代码，内附有说明-Very common color space transform VHDL code, containing a descr iption has