资源列表
ISP_FPGA_PAPER_04
- 视频扫描格式转换算法设计及其芯片实现.nh-Video scan format conversion algorithm and its chip. Nh
cnt10
- 一个用VHDL语言编写的十进制计数器，后续还有分频器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -VHDL language us
AD0809
- 基于FPGA的AD/DA控制VHDL程序-Based on the FPGA AD/DA control VHDL program
freq
- 本程序是基于vhdl语言的8位16进制频率计，待测频率范围是1HZ~100MHZ。-This procedure is based on the vhdl language 8 16 hex frequency, frequency range tested 1HZ ~ 100MHZ.
TXT2UCF
- 本软件为将PADS的原理图数据转换成FPGA软件引脚输入文件的软件。sch 转 ucf or tcl-The software for the schematic diagram of the PADS data into FPGA software pin input file . sch to ucf or tcl
HDVCSA.tar
- Hardware Decompression for Video Compressive Sensing Applications
FPGAPLL
- FPGA做的PLL 可以使用，比软件自带的省一些资源-PLL can be used FPGA to do more than the software comes with some of the resources of the province,
pdf417decode2.0
- 用于实现pdf417解码,二维码解码此系统可应用于需要对二维码进行识别的各种领域-pdf417decode,dimensional code decoding system can be applied to the need for two-dimensional code to identify the various areas, particularly
decoder
- 指令译码器的设计vhdl语言或者verilog HDL语言对单片机程序的处理-Instruction decoder design vhdl language or verilog HDL language processing microcomputer programs
EDAteaching
- 系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.
ep_rom
- 采用VerilogHdl语言编写的，介于FPGA的EPROM的开发读写-VerilogHdl the use of languages, ranging from the development of FPGA to read and write the EPROM
ALU
- 算数逻辑单元，实现算数加、减，加1、减1运算和逻辑与、或、非和传递-Arithmetic logic unit, to achieve arithmetic add, subtract, plus one, minus one operation and logical AND, OR, and transmission of non-