资源列表
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
Viraktamath_Agrawal
- matlab code for OFDM signal transmitted over an acoustic channel
function_automatic
- Verilog使用automatic function的範例-Verilog example of the use of the automatic function
USB_HID
- 全名的USB HID协议例子.包括HIDtoUARTExample MouseExample等例子-Full name of the USB HID protocol examples, including examples such HIDtoUARTExample MouseExample
stopwatch
- 此为秒表计数器的硬件描述语言源程序，有清零键和暂停键。该例子比较简单，适合初学者。有分频、十进制、六进制、秒表共四部分组成-This is the stopwatch counter hardware descr iption language source code , a clear key and the Pause button . The example is simple , suitable for beginners . Took part in the frequency ,
DDS_trans_final
- DDS芯片AD9854的配置文件，能配置正弦波的频率和幅度，也能配置相关的调制方式和调制参数，只要根据芯片资料给出合适的控制字入口参数即可，都是我在项目开发实际应用的代码，希望对大家有点帮助-AD9854 DDS chip, the configuration file, to configure the frequency and amplitude sine wave can also configure the relevant parameters of modulation and m
led_keyboard
- 用verilog语言实现键盘的移动扫描，这是基于ise实现的。 -Verilog language keyboard with a mobile scanner, which is based on the ise to achieve.
fpga_FILTER
- 基于FPGA的可编程数字滤波器系统,基于FPGA的数字滤波器的设计与实现,基于FPGA流水线分布式算法的FIR滤波器的实现-FPGA-based programmable digital filter system, the digital filter based on FPGA Design and Implementation, Distributed Pipelined FPGA-based FIR filter algorithm to achieve
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
Xil3S500E_revD_emac
- spartan 3e开发板中实现以太网通讯-spartan 3e development board Ethernet communications
flash_memory
- VHDL model for a NOR Flash
Verilog-HDL-intra_prediction
- 基于H.264的帧内预测中4×4块的9种预测方法的源程序-H.264 intra prediction based on 4 × 4 block prediction method of the source 9