资源列表
BOC
- 本文设计了一个区域卫星导航系统的BOC调制信号产生器，产生一个有BOC、C/A码、P码合成的信号-This design of a regional satellite navigation system BOC modulation signal generator to produce a BOC, C/A code, P code signal synthesis
SDRAM_CONTROLlER_Modelsim
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和文档-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
modelsim_crack
- ModelSim破解文件，本人实验通过（6.2K），没有问题,可以使用,内含使用说明-modelsim crack file
IS63LV1024L
- ISSI SRAM IS63LV1024L 时序仿真模型-Verilog model of IS63LV1024L
mux
- 多路选择器 verilog CPLD EPM1270 源代码-MUX source verilog CPLDEPM1270
standard
- CPU example from Altera. it is very usefu-CPU example from Altera. it is very usefull
ps2
- 采用sopc技术，nios2ide开发环境，实现nios对ps2键盘的控制，按键讲ascii码显示在led上-Using sopc technology, nios2ide development environment to achieve nios right ps2 keyboard control, key speakers led the ascii code is displayed in
adc_verilog
- 用verilog编写的ADC控制接口，只需根据具体ADC器件的时序图修改代码就可运行。-ADC prepared with verilog control interface, just depending on the ADC timing diagram of the device can modify the code to run.
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
sii9134
- Sii9134芯片的功能介绍，用于HDMI输出的编码-Features Sii9134 chip for HDMI output encoding
debounce_2_Verilog
- 用VerilogHDL编写的按键消抖程序 分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下后,产生时间为10ms的低电平信号,即LED亮10m-*Project Name :debounce *Module Name :debounce *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *Date : 2011-11-
temperature
- 使用FPGA控制18B20达到温度采集过程，并显示在数码管上。-Achieved using the FPGA control 18B20 temperature acquisition process and display the digital pipe.