资源列表
DE2_115_Audio
- NIOS2 实现音频代码,录音，听到声音-NIOS2 Audio
latch
- 关于闩锁效应的产生机理、触发条件、防止措施以及器件的闩锁测试的一个资料文件-This is a generation of latch-up mechanism , trigger conditions , measures and devices to prevent latch- test data file.
sin_cos_rom
- 9bit、512个数据点（1/4周期）的正弦余弦ROM查值表-9bit, 512 data points (1/4 cycle) check the value of the sine and cosine table ROM
inverter422
- 延时小，功耗小的反相器链设计。HSPICE 仿真网单，。25um工艺-less delay ,low power consumption.
vmm_exam
- vmm 验证方法学的学习实例（源代码），分步骤剖析整个验证设计过程-vmm verification methodology of learning examples (source code), the design process step by step analysis of the entire verification
led
- 基于fpga的流水灯仿真以及代码。 包含了整个过程。本人刚刚做过程序在quarter2下仿真成功！ -The water-based light simulation and fpga code. Includes the whole process. I just did the program under emulation in quarter2 success!
FIRde-verilog-shixian
- 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
freq_div
- 用verilog实现基于fpga的通用分频器，-Divider using verilog achieve common
eros
- 俄罗斯方块程序。-FPGA development board schematics
fifo_vhdl
- 基于vhdl语言实现的fifo控制器。经过仿真及实际测试-failed to translate
shizihong
- 用VHDL语言编写数字钟的程序，实现数字钟的几个功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
EDACLOCK
- 用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime