资源列表
RTL
- 256位有符号整数乘法器，个人学习时编写，接口为IPBUS，用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
ISE-12.3-Guide
- 本文为ise12.3详细开发步骤，对新手会非常有帮助的。-This article ise12.3 detailed development steps, the novice will be very helpful.
paobiao_gongyang
- 用verilog语言写的电子跑表，在共阳数码管上显示，八位的，初学EDA，感觉verilog语言好入门，我的QQ：942954258，欢迎与你共赢21世纪-Verilog language used to write electronic stopwatch, were positive in the digital display, eight, and novice EDA, started feeling good verilog language, my QQ: 942954258, w
key_sin
- PS/2键盘加DDS的verilog 设计-PS/2 keyboard plus the verilog design DDS
AD_9215
- 用Verilog实现AD9215驱动的开发-AD9215 with Verilog-driven development to achieve
ps2_fpga
- 键盘输入，在数码管显示对应按键的编码，从中了解键盘输入原理-Keyboard input, the digital display corresponds to the encoding keys
counter_0-to-9999
- 数码管计数，在数码管上计数，从0计到-Digital counting experiment, the digital count on, count from 0 to 9999
Learn-FPGA-through-example
- 深入浅出玩转FPGA(大量例程和PDF教程)-Learn FPGA through example
DF2C8_12_DS1302
- verilog实现DS1302时钟控制,程序已验证没有问题 -verilog achieve DS1302 clock control procedures have been verified there is no problem
nnARM01_11_1_3
- 包含详细的源代码，可以稍加修改就能应用在您的设计中-Contains detailed source code can be modified can be used in your design
Taxi-automatic
- 本项目实现一个出租车自动计费器。计费包括起步价、行车里程计费、等待时间计费三部分，用四位数码管显示总金额，最大值为999.9元。起步价为5.0元，3公里之内按起步价计费，超过3公里，每公里增加1元，等待时间单价为每1分钟0.1元。用两位数码管显示总里程，最大值为99公里，用两位数码管显示等待时间，最大值为99分钟。-The project achieved a taxi meter automatically. Billing, including starting, mileage charg
fifo_ex4
- 深入浅出玩转FPGA代码 实验四FIFO模块 基于EP1C3-Layman Fun FPGA code EP1C3 based experimental four FIFO modules