资源列表
bsconvert
- 基于FPGA的实现数据串并转换的程序，可以把8位串行数据转换为8位并行数据，或把8位并行数据转换为8位串行数据等-FPGA-based string and data conversion procedures, can be 8-bit serial data into 8-bit parallel data, or the 8-bit 8-bit parallel data into serial data
multifunction_clk
- 多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证-Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation
List.3DS-Proteus-ARES
- 3D Model to Proteus/ARES 3D PCB Visualization
divfreq
- 除頻器，用於數位電子乙級考試的時候，將主板上4MHZ的訊號進行除頻的硬體描述語言-Div Freq
deccount3
- 本程序是利用VHDL语言实现3分频器的设计-The program is 3 divider using VHDL language design
PS2-controller
- 基本AMBA APB总线的PS/2接口控制器，可以实现对PS/2键盘和鼠标的控制。-A PS/2 controller based on AMBA APB protocal,which can control the PS/2 keyboard and mouse.
MULTI8X8
- 乘法器的硬件快速实现，采用Vhdl语言，对于学习芯片开发的人有用。-multiply is completed by vhdl.
park
- 该程序是用VHDL制作的停车场停车位显示系统的源码-The program is produced with VHDL display system of parking spaces with source code
FPGA_Audio_Player
- Altera FPGA SD卡播放音乐程序，基于Nios，强力推荐！-Altera FPGA SD card music program, based on the Nios, highly recommended!
clk_sync
- 本文件是在ALTERA公司的QUARTUS下VHDL+原理图编写的时钟同步逻辑-This document is in the company' s QUARTUS ALTERA under VHDL+ schematic written clock synchronization logic
Hamming_Decoder
- (7,4)Hammming码解码器，verilog代码实现。监督矩阵为HT=[1,0,0 0,1,0 0,0,1 1,0,1 1,1,1 1,1,0 0,1,1]-(7,4) Hammming code decoder, verilog code. Monitoring matrix HT = [1,0,0 0,1,0 0,0,1 1,0,1 1,1,1 1,1,0 0,1,1]
UART
- verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用-verilog code for serial port transmit and receive code, with source code and test files, and accurate available