资源列表
adc8888
- 8位的a/d行为模型，可以应用于modelsim等环境下的仿真，不可综合。-eight of the a / d behavior model can be applied to other environments modelsim the simulation, not comprehensive.
sram__
- 静态随机读取存储器行为模型，可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
vga_verilog
- 本示例演示了VGA的控制方法，程序配置后可以在CRT上显示中文汉字等信息。-this example demonstrated the VGA control methods, procedures after the distribution of CRT Chinese characters on the show and other information.
PS2keyboard_verilog
- 本实验利用PS2接口实现了与键盘通信，并将键盘的按键编码通过UART接口上传给PC的超级终端，通过超级终端来观察按键编码是否正确。 -experimental use of the PS2 interface with the keyboard communications, and keyboard buttons coding through UART interface to the PC upload the Super Terminal, Super Terminal throug
lcd1621
- 在LCD上显示事先就输入好的字符,可以任意改变的-displayed on the LCD on the admission of prior good character, can be arbitrarily changed by the
JT2MIAN
- 交通灯控制,在A和B方向各用数码管显示剩余的时间.-control traffic lights in the direction of A and B of the digital show the remaining time.
digit_clock
- FPGA设计的时钟！很特别，本人的第一次，还望各位探讨！-FPGA design the clock! Very special, the first time I also hope to explore!
atlrallianxi
- atlral初学练习 vhdl实例联系-atlral novice practice examples linked vhdl
chengxufengxiang
- 这些程序我用MAX+PlusII软件测试均能通过编译，程序本身不复杂，旨在为刚接触VHDL语言的朋友提供一些样例，以便了解VHDL语言的基本构成。如果要运行测试，则新建文件名应于程序中实体名一致，文件后缀“.vhd”，不推荐直接通过复制、粘贴的方法录入程序，可能会引入错误字符。 -these procedures I used MAX PlusII Software Testing pass compiler, the process itself is not complicated. for
lzhu
- 自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲-wrote it myself
ddssheji
- 这是用VHDL语言编写的一个DDS频率合成器的源程序-VHDL prepared a DDS DDS source
PushButton_Debouncer
- KEY INPUT DEBUNCE VERILOG-KEY INPUT DEBUNCE verilog