资源列表
std_cf_1c20
- Altera公司开发板1c20 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 1c20 CF cartoon with routines (initialization, reading, writing, testing, etc.)
std_cf_1s40
- Altera公司开发板1s40 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 1s40 CF cartoon with routines (initialization, reading, writing, testing, etc.)
std_cf_2s60_ES
- Altera公司开发板2s60 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 2s60 CF cartoon with routines (initialization, reading, writing, testing, etc.)
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
VHDL.fifo
- 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
tom08
- SRAM 视频采集测试程序 读写时序控制 为解决时钟切换而做的测试程序-SRAM test sequential read and write control procedures to resolve the clock switching out of the test procedure
fft_512
- 由system generator生成，可供参考-generator generated by the system is available for reference,
fq_divider
- 分频器-Divider ..
interpolation_FIR
- Interpolation FIR Design Example for Stratix Devices
fir-vhdl
- 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Descr iption Languages in preparing the FIR digital filter
miaobiao_watch
- 此为秒表程序，具有秒表的一般基本功能，已在MAX+plusII 10.2下编译通过。-stopwatch for this procedure is the general basic stopwatch functions, MAX has been under plusII 10.2 compile.
8251_8055_verilog
- 8251和8055的verilog源码，可进行综合和仿真，是学习SOC的好资料！-8251 and 8055 verilog the source, and integrated simulation, SOC is a good learning information!