资源列表
equalizer
- matlab code for ZF equalizer
VHDL-和-Verilog-HDL-的区别
- The difference between VHDL and Verilog HDL.
计算器
- 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)
Desktop
- 实现了3-8译码器的组合逻辑和时序逻辑，正确性已经通过了仿真验证，代码规范(The combined logic and timing logic of the 3-8 decoders are implemented. The correctness has already passed through the simulation verification, the code specification)
spi
- 实现spi写功能，读功能，仿真，板级调试都通过验证了。(achieve write function and read function of spi, simulation is verified)
FIR_filter_stereotype
- 第二类有限冲击响应滤波器60阶常系数verilog(The second type of finite impulse response filter, 60 order,coefficient verilog)
fifo
- IL SAGIT D'UN FIFO EN DEscr iptION DE LANGUAGE vhdl
EthCRC32
- This module calculates ethernet crc32 on fpga using table method
ACC_CarryIn_CarryOut
- This module does Accumulate operation used in dsp. Tested on fpga.
xujiance
- 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
txrx
- FPGA串口通信的简单示例程序，分为TX和RX两个模块(A simple program for FPGA serial communication)
ADC0804
- 控制ADC0804的verilog 代码，cpld/fpga都可以使用，用数码管显示ADC采集的二进制数据。(Control ADC0804 verilog code, cpld / fpga can be used to display the ADC digital tube with the binary data collected.)