资源列表
AD_TO_FIFO
- A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)
hmc960
- hmc960芯片的初始化程序，可以实现verilog程序，微波信号的放大(hmc960 initial code,spi ,verilog,amplify)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
Carry-Skip Adder
- 经典的进位跳跃、进位选择、并行前缀加法器，16位，基于verilog HDL语言(16-bit carry-skip adder)
y210
- 三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)
clock1
- 时钟显示程序，EDA实验，用verilog语言编写(EDA experiment with verilog language)
key_filter
- Verilog实现按键滤波，亲测可用，有需要的可以下载看看(Verilog to achieve key filter)
mux_2to1_4to1_8to1
- design verilog hdl for mux 2to1, mux4to1, mux8to1
uart_control
- UART接口的读写，8bit数据位，无停止位(UART interface read and write, 8bit data bits, no stop bit)
second
- 等精度测试，待测频率超过100就停止产生脉冲(Such as precision testing, more than 100 stopped produce pulse frequency under test)
cic3s32
- 3阶cic滤波器，16位输出，32倍降采样处理(The 3 order CIC filter, 16 bit output, 32 fold down sampling processing)
music
- implement a musis player