资源列表
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
ffirr_166i
- fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 -fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
VPD__using_FFe
- verilog开发一种种基于fpga的鉴相器模块 -the verilog development of all kinds based on fpga phase detector module
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
Ts3cc2410PPLLh
- 这个是三星arm9芯片的PLLL源码，不可多的啊 -This is the Samsung arm9 chip the PLLL source can not be more
FDDDDSPLLP
- 一种基于FPGA的新的的DDS+PLL时钟发生器 -An FPGA-based new DDS+PLL clock generator
TCOLLOR_CHAR_h
- 此ip核是xvga视频接口控制器，，主要针对xilinx公司的开发工具 -This IP core is the xvga video interface controller, the main development tool for xilinx
IDCTTzipm
- 改进的DCT算法设计，，veriloghdl实现 -Improve the DCT algorithm design,, veriloghdl to achieve
FffppgajpegP
- 一种基于FPGA的JJPEG图像压缩芯片设计 -Based the FPGA JJPEG image compression chip design
DDDCCT_IDCTi
- 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包含VHDL及及Verilog版本。可用途JPEG及MEPG压缩算法 已通过测试。 -The discrete cosine transform and inverse discrete cosine transform HDL code and test files. Contains VHDL and Verilog versions. Can use JPEG and MEPG compression of algorithm has
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- change path LED8X8 多圖切換-change path led8x8 path change