资源列表
pinlvji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
ssji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
ssaszhaohengji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
VGAverilog
- VGA scanning programm
stack
- stack code for fpga..using verilog
HDB3(verilog)
- HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看-HDB3_verilog coding procedures
verilog-compiler
- 本文包含了几个关于Verilog的编译器的源码实现，适用于深入学习Verilog的读者-This article contains several Verilog compiler source for in-depth study of Verilog reader
IMGcolor
- 采用VHDL语言写的VGA屏幕显示控制程序，通过电阻分压网络可以显示256种颜色，并可以在屏幕上移动。-Using VHDL language VGA screen display control program can display 256 colors, and can move on the screen through a resistor divider network.
DAC.cmp
- 可编程逻辑器件CPLD/FPGA 该实验系统采用了独特的设计技术，使得实验用的可编程CPLD/FPGA 器件的I/O 接口与系统的相关器件采用固定连接-The programmable logic device CPLD/FPGA The experimental system uses a unique design technology, making the experiment with the programmable CPLD/FPGA device I/O interface wi
adder
- 加法器设计，详细的设计步骤-Adder design, detailed design steps
divider
- 除法器设计，有详细的步骤-Design of divider, detailed steps
mul
- 伽罗华域GF（q）乘法器 有详细的步骤-Galois field ( q ) multiplierer