资源列表
1G-NANDP1G-DDR3-(Rev_01)
- 1G Bit (129Mx8) Nand flash / 1G Bit (8Mx16x8Banks) DDR3 SDRAM
Projet_Sahar2
- wdt for watermarking image in vhdl code
rs2
- 我自己做的rs 编解码，里面有全套的程序，已经运行通过，可以放心使用-I do rs codec, which has a full range of program has been run through, you can rest assured that use
crc
- CRC校验原理，详细讲述CRC的数学模型和计算机实现-The CRC principles, a detailed account of the CRC mathematical models and computer implementation
FPGA_Turbo
- Turbo码编解码的FPGA实现，verilog语言编写-Implementation ofTurbo code on FPGA , using Verilog language
RTL
- 频率检测模块，停止检测可设10K~100K，低频检测1M，高频检测5M。用于7816通讯模块-Frequency detection module, the stop detection can be set to 10K to 100K, low-frequency detection 1M, high-frequency detection 5M. For 7816 communication module
The-state-machine-sequence-detector
- 状态机实现序列检测器。设计一个一个左移移位寄存器，用硬件设备上的两个拔码开关，预置一个8位二进制数作为待检测码，随着时钟逐步输入序列检测器，8个脉冲后检测器输出结果。-The state machine sequence detector. Design a left shift register, two on the hardware DIP switch and preset an 8-bit binary number as to be detected code, as the clo
Convolution-report
- 卷积码编解码器实现报告 包括 目的 要求 内容 代码 总结等-Convolutional encoding and decoding the report, including the purpose of the request content code summary
sd_hd_sdi_good_using_micro8_CPU
- 美国Lattice公司的FPGA上实现的标清高清串行数字接口SDI的程序，使用到Micro8处理器，可以综合。-lattice FPGA to achieve the standard definition high-definition serial digital interface SDI program, the use of Micro8 processor on the FPGA.
fpga
- 18b20基于fpga对温度进行数码管的显示-18b20 fpga
mi_ma_suo
- 采用quartusii_6.0编写的，基于FPGA的密码锁系统，分模块设计。-Using quartusii_6.0 write locks FPGA-based system, modular design.
17_parity
- 奇偶校验器，对八位二进制数据及其奇偶校验位的输入进行校验，输出正确的奇偶校验位。-Parity, eight binary data and its parity bit input calibration, and output the correct parity bit.