资源列表
T65_v302
- VHDL source codes of a 65xx compatible cpu core. Version 302.
verilog-digitaldesign
- Verilog digital design
guanyuqichezuoweidengkongzhi
- 基于verilogHDL的控制汽车左尾灯的程序。有些问题，需要向高手请教。-Based on the verilogHDL control car left taillight program.Some questions need to consult, master.
Interrupt-priority-levels
- 用流水灯或数码管显示实现8051芯片的中断优先级功能。-Lamp or water pipe with a digital display of 8051 s interrupt priority feature.
opencpu32
- OPENCCPU 32 bits/Nã o é possível projetar sistemas digitais sem entender alguns blocos básicos, tais como portas lógicas e flip-flops. A maioria dos circuitos digitais baseados em portas lógicas e flip-flops é normalmente projetada a partir d
blocking
- 基于verilog语言的数据选择器，包括数据选择器的测试模块 -verilog language based on the data selector, including data selection for the test module
cpc1
- 实现序列检测的功能，对特定数字序列成功的检测-Achieve the function of sequence detection for detecting the success of a particular sequence of numbers
xapp463_verilog
- xilinx xapp you have a good lock.
Sine-wave-generator
- 正弦波发生器 利用直接数值合成DDS原理驱动DAC0832实现正弦波输出-Sine wave generator using direct numerical synthesis of theory-driven DAC0832 achieve DDS sine wave output
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
vhdl-clock-with-vga-output-for-Nexys-2
- Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.