资源列表
fp_prj
- 这是自己编写的一个流水灯程序 通过修改cs的值可实现方向的翻转 但是没有接入案件功能 需要的同学可自行添加 使用quartus12编译 modelsim10.1仿真-This is a program I have written a light water can be achieved by modifying the value of cs direction flip but no access cases feature requires students own add use qu
verilog
- 用verilog编写的实用电话计费器程序 -The telephone billing procedures written in verilog
S16_ADC_NEW
- ADC7923的verilog程序，spi配置的，测试可用-ADC7923 verilog program, spi configuration, testing available
fir
- 16阶的FIR滤波器的verilog文件，包含了测试报告。-16 order FIR filter verilog file contains a test report.
DDSFPGA
- 在fpga中实现的DDS程序，程序，测试可用-DDS program, implemented in fpga program, the test can be used
stack_16x8
- VHDL语言写的16x8堆栈模块设计，存储器全满时给出信号并拒绝继续存入；读出时按后进先出原则；存储数据一旦读出就从存储器中消失；有相应的testbech文件，经测试可用。对小型设计很有用！欢迎下载交流学习。-Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out
fpgaUPDW
- fpga上下变频混频实现，其中CIC采用多种方法设计，自己花两个星期编写，中文注释，浅显易懂-fpga up and down conversion mixer implemented which CIC using a variety of methods designed, he spent two weeks writing notes in Chinese, easy to understand
MS-final-project
- DLX 5级流水 实现所有功能 包括跳转指令-DLX 5 stage pipeline to achieve all functions including jump instruction
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
FPGA_CPLD-SHC
- FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考-FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design
lcd3
- FPGA驱动lcd1602代码，使用标准三段式状态机编写-FPGA LCD code
DAbx
- 基于FPGA的并行FIR数字滤波器的实现-FPGA-based parallel FIR digital filter implementation