资源列表
pnsequence.v
- pn sequence generator in verilog
FPGA
- 基于FPGA的视觉电生理图像刺激系统的设计-Based on the design of FPGA visual electrophysiology image stimulation system
Keyb27Seg
- VHDL codes for Multiplexed 7 segment LED, verified for Spartan3E (Basys2) FPGA board. This is part of Digital System Design course at Fasilkom UI.
frequency---base-on-verilog
- 基于verilog的数字频率计设计(源码)-frequency design base on verilog
divid_frequency_7
- 实现对输入时钟的7分频处理。使用计数器，对输入时钟进行了分频，但这样存在缺陷，有可能造成输出时钟的不稳定。-Seven points of the input clock frequency processing. Counter, on the clock input of a frequency dividing, but such defects, it may cause instability of the output clock.
divid_frequency_16
- 使用计数器，对输入时钟进行了分频，但这样存在缺陷，有可能造成输出时钟的不稳定。-Counter, on the clock input of a frequency dividing, but such defects, it may cause instability of the output clock.
M31serial
- 码长为31的M序列产生器，实现码长为31的M序列发生器的功能-Code length of 31 M-sequence generator, the code length of 31 in the M-sequence generator function
selector3to1
- 三选一数据选择器，完成三个中选一个出口的功能，可以根据需要，进行改编-Three data selector, completed a three selected export function may need to adapt
contador-caso-especial-y-procedimientos
- contadores y ejemplos de diseñ o en verilog
PARITY-CHECK
- this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check
n-bit
- n bit parity generator is a versatile program that adds parity bits for any length of data the user enters . It accurately adds parity bits on the MSB and solves the problem during any kind of digital communication protocol
lcd_dis_ok
- lcd液晶显示屏驱动程序，在fpga开发板上使用，欢迎下载使用。-LCD driver lcd fpga development board, welcome to download.