资源列表
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
pwm_test
- 本程序演示了PWM技术,通过调节脉宽控制输出电压,从而控制电机的转速-This program demonstrates the PWM technique to control the output voltage by adjusting the pulse width to control the motor speed
NIOS_USBHOST
- FPGA QUARTUS USB设备通讯模块程序，常用模块。-FPGA QUARTUS USB devive module ,embeded device.
halfclk
- 本代码功能为实现输入时钟的1.5分频功能。 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions as the input clock fre
binary-to-decimalno.
- Vhdl code for binary to decimal conversion
cpld_zaixianxiazai_danpianji_cankao
- 单片机对CPLD在线编程参考——中文 .pdf-CPLD programming on-line single-chip reference- in Chinese. Pdf
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
vhdl
- basics of language vhdl , how it operates etc can be laernt
coding_and_synthesis_with_verilog
- In the semiconductor and electronic design industry, Verilog is a hardware descr iption language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verificati
EDA_2
- 简易计算器，可四位同时显示，加减法有指示-Simple calculator four also showed that addition and subtraction with instructions
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
fifo
- 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.