资源列表
veriloghdl
- 几个Verilong的例子程序，初学者可以用来参考-Several examples of Verilong program for beginners can be used to refer to
trunk
- code for adaptive lms equilizer
system05_latest.tar
- 6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz
shr_spi3.tar
- cadence环境下的spi3接口实现，包含源代码和仿真文件-SPI3 interface under cadence， include the source file and the simulation file
divider
- verilog divider hardware
eeprom_test
- stc eeprom_test 内部flash读写操作源码-stc eeprom_test read/write code program
20077713594628186
- 基于 vhdl环境的程序 多路抢搭起
license
- license modelsim xilinx
pdiv
- 数控分频器的功能是，当在输入端给定不同的输入数据时，对于输入的时钟信号有不同的分频比。-The function of this divider is when different input data is available at the input,there is different divider ratio for clk.
11114
- 秒表功能的显示 LCD1602显示,自动加1 VHDL -SECOND WATCH 测试通过
196947shizilu
- 使用VHDL实现十字路*通灯控制器设计，适用于初学者-The realization of the use of VHDL crossroads traffic lights controller design for beginners
SCH_FPGA
- lattice XP FPGA开发板原理图，由Lattice代理商开发-Lattice XP FPGA demo schematic