资源列表
fpga_assignment1
- 这是由简单串行转并行的一个verlog程序，还带testbench，有一张仿真的图片在里面。软件用的是Quartus II9.1 Web Edition。-This is from the simple serial turn a verlog parallel programs, but also bring testbench, and a simulation pictures in it. Software is used II9.1 Web Quartus happen.
DW8051_core
- 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
VERILOG_VERSION_PIC16C57
- VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
Battery
- 关于直流电源监控系统的电池自动内阻检测程序-Battery internal resistance testing procedures
1.2-led_change
- verilog代码控制led改变 使用xlinx开发平台-led_change verilog
ex1
- 设计一个循环灯控制器，该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。（假设外部提供频率为1MHz的方波信号） 编程环境为Quartus II 11.0 仿真环境为 Modelsim 6.6d 通过仿真可以看出。系统复位后，红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒，三个发光管循环发亮。 -Design a loop lamp controller that controls the red, green and ye
FPGA-zhengqie
- 可以考虑利用FPGA来构成系统检测获取偏振图像的Stokes矢量，而 由Stokes矢量来计算偏振角利用FPGA实现就比较复杂，往往又利用软件来实现，这 与最初利用FPGA硬件实现偏振图像的Stokes矢量计算达到实时性要求的初衷不符， 因此有必要设计出一种利用FPGA来硬件实现actan函数的计算的方法。 -Can be considered to constitute a system test using FPGA to obtain polarization images
HEX_1F
- 本实验的功能为：每过一秒，阴极数码管从0循环演变到F-The function of this experiment as follows: with each passing second, cathodic evolution of the digital control loop from 0 to F
EDA-xiti
- 由12进制和60进制计数器组成的时钟电路。-12 229 and 60 binary counter clock circuit.
freq
- 应用VHDL语言设计低频数字频率计，选择测频法方案，主要是控制电路，由其产生闸门、清零和锁存等信号。-VHDL, design low frequency digital frequency meter, select the frequency method to program, mainly the control circuit, produced by the gate and the latch so clear signal.
good
- 《无线通信FPGA设计》一书中例子的Matlab及verilog代码-" Wireless FPGA Design," a book example of Matlab and verilog code
caideng
- 这个程序是用verilog语言编写的彩灯的小程序，使用状态机来实现，可以实现多种花型，有具体的程序！-This program is written in verilog small lantern, the use of state machine, you can achieve a variety of flowers, there are specific procedures!