资源列表
verilogpinlvji
- 这是一个已经仿真过的在FPGA上用Verilog编写的用于测量频率源代码-A simulation on FPGA using Verilog the for measuring frequency source code written
part1
- Altera DE2 开发板试验2 第1部分VHDL答案-Altera DE2 Lab2 part1 VHDL answer
spi_cpld_vhdl
- The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of S
DA_TLC5620_vhdl
- 这是一个用TLC5620DA芯片作数模转换的FPGA编程程序，采用的语言为VHDL-This is an FPGA programming procedures TLC5620DA chip a comprehensive and balanced analog conversion, the language used is VHDL
counter
- generating counter using VHDL
UNI-T_signal
- 普源示波器自带信号测试版，CPLD实现，产生方波、三角波、锯齿波等信号-RIGOL signal beta, CPLD implementation, generate a square wave, triangle wave, sawtooth and other signals
FPGAshiyan(11)
- FPGA入门系列实验教程——实验十一数码管动态显示-Getting Started with FPGA tutorial series of experiments- Experiment XI LED dynamic display
jiaotongdeng
- 交通灯1．设计一个十字路口的交通灯控制电路，要求 甲车道和乙车道两条交叉道路上的车辆交替 运行， 每次通行时间都设为25秒； 2．要求黄灯先亮5秒，才能变换运行车道； 3．黄灯亮时，要求每秒钟闪亮一次 。-jiaotongdeng
zhuangtaiji
- 状态机 多种状态的转换 verilog语言编写-Convert verilog language write state machine multiple states
VHDL-32bit-add
- 功能实现：“1015+1016+1017+...+1115” 101个数的累加（1s/次） 数码管显示结果，结果为1015、2031、3048、40-The functions: " 1015+1016+1017+ the ...+1115" 101 the number of cumulative (1s/time) digital tube display results, results 1015,2031,3048,4066 ...
car
- 基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器-Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors
top1
- 七段数码管译码器，可显示0~9共10个字符。(Seven segment digital decoder, 0~9 can display a total of 10 characters.)