资源列表
VGA_char
- Verilog语言描述的VGA显示实验，主要目的是在屏幕上显示不同的字符，Quartus 10 中编译通过。-Verilog language descr iption of the VGA display experiment, the main purpose is to display different characters on the screen, Quartus 10 in the compile.
miaobiao
- 本人自编的秒表，有十进制模块，六进制模块以及进位控制模块，并有电路连接图。-I am self stopwatch, a decimal module, hexadecimal and binary module control module, and a circuit with Have set.
FPGA-PWM_LED
- FPGA 实现PWM控制LED的例程 具有参考意义-FPGA to achieve LED PWM control routine
ll
- 电子计数器测频有两种方式：一是直接测频法，即在一定闸门时间内测量被测信号的脉冲个数；二是间接测频法，如周期测频法。直接测频法适用于高频信号的频率测量，间接测频法适用于低频信号的频率测量。本文阐述了用数字电路设计了一个简单的数字频率计的过程。-Electronic counter measuring frequency in two ways: one is the direct frequency measurement method, that is, in a certain gate ti
13
- 串口学习小程序，有点verilong背景 就能看懂-fpga verilong
ALU
- this is a 4 bit alu design-this is a 4 bit alu design
add_tree
- 本程序为加法树乘法器，计算16位读写地址，应用于LCD CSTN驱动芯片设计的SRAM的读写控制-This procedure for the adder tree multiplier, calculated 16-bit read and write address, used in LCD CSTN driver IC designed to control the SRAM s read and write
HDB3
- VHDL语言编写的HDB3码的编译码模块-VHDL language code HDB3 codec module
DE1_Default
- DE1开发板案例，开发板附带代码3，DE1_Default.rar-DE1 development board case, the development board with the code 3 DE1_Default.rar
adc0804
- 这个是经典的0804的ad传感器的驱动代码，已调可用，并且真的是非常经典-This is a classic ad sensor driver code 0804, the modulated available and really is very classic
DigLockLoop
- VHDL设计的数字锁相环，可供设计参考。-digtal lock phase loop。
clock
- verilog 秒表程序（quartus ii8.2 ep2c5）-clock