资源列表
1024FFT-verilog-hdl
- 基于spartan 3e 的IFFT算法verilog HDL程序-Based on the verilog 3e Spartan IFFT algorithm of HDL program
AIC23_Configure_Test
- 用verilog写的关于AIC23的配置程序，在板子上已经验证通过。-Verilog to write about AIC23 configuration program, the board has been verified.
Weighted-Round-Robin-Arbiter-master
- 带权重的优先级轮转算法的verilog实现(Verilog implementation of priority rotation algorithm with weight)
fenpinqi
- 基于VHDL 语言的分频器设计， EDA； CPLD； VHDL； 仿真-Divider based on VHDL language design, EDA CPLD VHDL Simulation
Clock_Full
- clock program on altera de2-70 board
cyc2_cii51005
- for Cyclone II FPGA
jiaotongdeng
- 状态机实现十字路口的交通灯红黄绿 代码中用八位的led高三位灯分别表示a路口的红黄绿低三位表示b路口的红黄绿-State machine to achieve the crossroads of traffic lights red yellow and green code with eight high three LED lights denote a junction of red, yellow, and green the lower three b junction of red
cpld_dsk
- TMS320C6416T DSK开发板的CPLD源程序，经测试编译通过并且下载成功。
VGA
- VGA实验 FPGA Design - Best Practices- FPGA Design- Best Practices
dpll
- 本工程为锁相环，采用全数字系统设计，输出频率在10M~100M之间！可改进。-This project is phase-locked loop, all-digital system design, the output frequency between the 10M ~ 100M! Can be improved.
crc
- 基于FPGA VerilogHDL 的crc的算法。-Crc algorithm based on FPGA VerilogHDL.
fft16_vhdl
- 16位FFT，含测试，VHDL，浮点FFT算法-FFT-16，VHDL