资源列表
ADPCMCodec
- The DVI Adaptive Differential Pulse Code Modulation (ADPCM) algorithm was first described in an IMA recommendation on audio formats and conversion practices [1]. ADPCM is a transformation that encodes 16-bit audio as 4 bits (a 4:1 compression ratio).
iic_top
- iic协议的功能实现verilog HDL代码，并用7段数码管进行验证，压缩包内含有整个工程文件。-function iic protocol implementation verilog HDL code and seven-segment LED to verify, compressed package file containing the entire project.
1002
- median filter algorithm help
liangzu
- 一小段梁祝音乐播放范例的文件，希望对学习verilog的初学者有所帮助。-Butterfly short sample music files, want to learn verilog beginner help.
cqjw_add(2010-4-08)
- 实现文本文件的读入，并对读入的数据进行累加。-function：implement the adder
FIFO
- FIFO的设计，用Verilog HDL语言编写-The design of FIFO,using Verilog HDL program language
0702
- 七段数码管显示数字时 使用VHDL语言编写-VHDL The seven-segment LED display digital clock
16bit_cpu
- 16位的RISC_CPU， 应该对大家有帮助
segm01
- 8位数码管显示 通用型，只要输入32位的对应数据就可以使用-8 segms display
FourBitsCounter
- 四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model
Song-playback-circuit-design-VHDL
- 乐曲播放电路VHDL设计 附仿真报告、顶层文件和源程序-Song playback circuit design VHDL simulation report attached, and the top-level source file
DM10_KX8051_LCD128X64_C5T
- FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD