资源列表
music
- verilog实现FPGA板的音乐播放功能，可调整不同乐谱-Verilog FPGA board music player, adjustable sheet music
8_VGA
- 基于EP2C8Q208C8N的vga程序，对于入门FPGA有帮助-Based EP2C8Q208C8N the vga procedures for entry FPGA helpful
8947362452
- FPGA控制AD采集全过程的VHDL程序-FPGA controls the whole process of collecting AD VHDL program
DDC_VHDL
- DDS信号发生器，可以生成方波，三角波以及正正弦波等，只要稍微修改下输入数据即可生成任意的波形。-DDS signal generator can generate a square wave, and some small modifications to the next input data to generate arbitrary waveforms.
13_smg_interface_demo
- 计时器，并使用数码管来显示。计数程序产生一个６位的十进制的计数器，个位的计数为 100ms, 个位计到９进位，所以十位的计数为１s, 百位为 10s, 依次类推(A timer, and a digital tube to display.The counting program produces a 6 bit decimal counter, the number of bits is 100ms, the bit is 9, so the count of the ten bits is
step_motor_fenpin
- 步进电机驱动，采用Verilog语言分频法设计，可实现一直转动。-Stepper motor drive, using Verilog language crossover method designed to achieve has been rotated.
44key-pad
- 用verilog hdl语言实现4*4键盘扫描的小程序-With the verilog hdl language 4* 4 keyboard scan applet
wave_zhankongbi
- 基于quartus2的PWM波源代码。。 调频范围：1hz至100khz。。。很准-The PWM wave source code based on quartus2. . . . Frequency range: 1hz to 100khz. . . Is quasi-
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
modelsim
- modelsim開發 用於CABAC解碼-I don t konw
12chuankou
- fpga 串口调试小程序 可以收发，简单明了-fpga progra
source
- SDRAM 控制, 用於SDRAM上 的代碼-SDRAM Control