资源列表
05702277
- vhdl code by jaswant singh
LED11511
- FPGA 控制LED的verilog程序 十分适合新手学习-FPGA LED control verilog program stutable for newbies
ex5_mux
- 乘法器是众多数字系统中的基本模块。 从原理上说它属于组合逻辑范畴；但从工程实际设计上来说，它往往会利用时序逻辑设计的方法来实现，属于时序逻辑的范畴。通过这个实验使大家能够掌握利用 FPGA/CPLD 设计乘法器的思想，并且能够将我们设计的乘法器应用到实际工程中。 -The multiplier is the number of a digital system in the basic module. From the principle that it belongs to the combi
steppermotor
- 步进电机驱动程序 使用verilog语言，简单易学 留作参考-Stepper motor driver using the Verilog language, easy to learn for reference
clock1
- 本程序用VHDL编写数字钟，具有定点报时，手动调整时间等功能，能下载到板子上显示时间。-This program written by VHDL digital clock, with a fixed broadcast, manually adjust the time and other functions, can be downloaded to display the time on the board.
crc
- 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
mux
- 利用velilog语言，进行乘法器的设计-velilog language, multiplier design
fenpin
- FPGA 控制步进电机 采用分频发设计控制端-Frequent FPGA to control stepping motor points
VHDLPFIR
- 基于VHDL的FIR滤波器设计。详细讲了用硬件设计FIR滤波器！-The FIR filter design based on VHDL. Details about the hardware design of FIR filters with!
dianziqin
- 用VERILOG编写的 电子琴程序 顶层使用图形模块化连接 思路清晰。-Procedures for the preparation of the flower with the VERILOG top of a graphical modular connection clear thinking.
Syn_FIFO(wanzheng)
- 基于IPcore的同步FIFO的编写。读写数据位宽都为8bit，深度为32.-Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
VGA_interface
- 采用FPGA控制VGA的借口，采用Verilog编写，Quartus II编译，恰当配置后开发板可以与显示器相连显示图像-Using FPGA to control VGA excuse, Verilog prepared, Quartus II compilation, the proper development board can be configured to display an image attached to the monitor