资源列表
VHDL-Code-For-Half-Adder-By-Data-Flow-Modeling.zi
- VHDL Code For Half Adder By Data Flow Modeling
Stage3_3175133_Zhang
- 用MATLAB里的XILINX BLOCKS, 支持FPGA算法, 实现X_NEXT = ((n-1)x+ A/x(n-1)次)/n
freq-counter
- 基于测频法的频率计，以STC89C52单片机为核心构成单片机应用系统。-Frequency measurement method based on the frequency counter to the core composition STC89C52 microcontroller chip applications.
verilogdct
- dct实现verilog hdl的数字图像处理，源代码-dct achieve verilog hdl digital image processing, source code
mux21
- 二选一选择器的Verilog的实现。二输入，一片选段。-realization of mux21
Guia_1B
- 0-10-0 counter to 8051 microcontroller in assembly
dayashankar_nair_verilog_1.3.tar
- verilog assignments one
DE2-115引脚分配
- DE2-115引脚分配说明，使用时查找十分方便。(DE2-115 pin assignment descr iption)
ppm编解码器
- 进行ppm编解码的verilog代码，RTL描述(Verilog code for ppm encoding and decoding, RTL descr iption)
EDA-2
- 数字电子技术基础课程的第二次EDA作业，内容是投币充电仪。(The second EDA assignment of basic course of digital electronic technology is coin charger.)
T65_v301
- 微处理器核源码 like 6050 单片机-source like nuclear microprocessor 6050 MCU
MIT_MIPS_Core.tar
- 麻省理工的一个实验室实现的MIPS IP CORE，可以在FPGA上跑通 -a Massachusetts Institute of Technology laboratory achieved MIPS IP CORE, the FPGA can run on Link