资源列表
mult_16
- 用verilog实现对三个16位数进行相加乘法器-Three 16-digit sum of the multiplier Verilog
uart
- verilog VHDL实现的DE2 uart-Verilog VHDL the uart of the DE2
dianzibiao
- 电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块-module clock(clk,rst,clock_en,second,minute,hour) input clk,rst,clock_en output[5:0]second,minute,hour reg[5:0]second,minute,hour
Attachments_2012_06_19
- verilog basic materials-verilog basic materials
FPGA-development--and-VHDL--based
- FPGA开发流程简介与Verilog HDL语言基础-FPGA development process and VHDL language based
8.8_FPGA
- 关于简略通用异步收发器设计描述，有些细节描述或许不太清楚-Described briefly Universal Asynchronous Receiver Transmitter design, some detail may be less clear
pinlvji
- 使用verilog语言设计一个3位十进制数字式频率计，其测量范围为1MHz，量程为10kMz,100kMz和1MMz三档（最大读数分别为：9.99kMz，99.9kMz和999kMz）-Use verilog language, design a three decimal digital frequency meter
QuartusII
- QuartusII 相当全的文件，不能错过哦。-QuartusII users must save it!
4BITMULT
- 基于FPGA的四位乘法器，在QuartusII上编译通过可实现，采用VHDL语言编写。-Based on FPGA four on time-multiplier, in QuartusII compiled can be realized through, the VHDL language.
CODER
- 基于FPGA的8线-3线优先编码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA eight line-3 line is preferred encoder design, QuartusII compile, USES the VHDL language.
DECODER7
- 基于FPGA的BCD/七段译码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA BCD/these seven decoder design, QuartusII compile, USES the VHDL language.
adder
- 基于FPGA的加法器的设计，QuartusII编译通过，采用VHDL语言编写。-The adder on FPGA design, QuartusII compile, USES the VHDL language.