资源列表
DE2_TV
- 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
VHDL-example
- VHDL的几个实用例程，能帮助开发工程的同学更好的完成项目。-Several practical VHDL routines to help students develop a better project to complete the project.
PWMnios
- niosPWM可以在SOPC builder中实现PWM功能的自定制，通过PWM口可实现对电机的调速。-niosPWM SOPC builder can achieve PWM function of customized, PWM through the mouth can be realized right motor speed control.
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
i2c_code
- I2C protocol which as been verified and tested using testbench
lcd1602
- lcd1602芯片实现单片机显示 使用硬件描述语言，程序已经经过调试，可成功运行-lcd display
sdram_vhdl
- VHDL实现的读取和写入SDRAM的程序代码，学习的人可以参考下-VHDL implementation SDRAM read and write program code, can refer to the following study
Grayscale-Conversion-IP
- Sobel Edge Detection IP for FPGA using LABVIEW
e2fmt.tar
- edif to blif FPGA research application used to convert edif file formats to blif
PS2_IP_CORE
- 该IP核是一个ps2键盘的源代码（vhdl语言）-The IP core is a ps2 keyboard source code (vhdl language)
ji-shu-qi
- fpga 本例程为加减法计数器，主要实现的加减法计数的功能-fpga counter the routine for the addition and subtraction, addition and subtraction to achieve the main function of count
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE