资源列表
fujitsuPR_FINAL
- OMNIVISION DEMONSTRATES LATEST OMNIBSI 8MEGAPIXEL SOLUTION AT MOBILE WORLD CONGRE-OMNIVISION DEMONSTRATES LATEST OMNIBSI 8MEGAPIXEL SOLUTION AT MOBILE WORLD CONGRESS
watch
- 用VHDL设计实现秒表功能：秒表功能包括开始/暂停键和清零键，精度要达到0.01秒，所以计数显示共有八个数码管，而每个数码管又有八个管脚，因此采用扫描显示的方法，减少管脚数量。时钟脉冲由最低位给入，采用异步方式驱动更高位的计数，时钟频率应该为100Hz，通过数码管显示，共有八个数码管，所以扫描频率应在100Hz的8倍以上。（付按键消抖代码）-VHDL design with a stopwatch functions: stopwatch features include Start/PAUSE
S2P_xapp194
- VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
SerialtoParallelConverter
- 串行转并行SerialtoParallelConverter
Micro16-30sep03
- Micro16 - 一个简单的 16 位 VHDL CPU 核源代码-Micro16- A Simple 16 bit VHDL CPU source code
example6
- 按键控制加减及消抖：使用KEY1和KEY2控制数据的加减。-Key control and eliminate buffeting Modified: KEY1 and KEY2 control data using addition and subtraction.
miaobiao-design_Verilog_HDL
- 秒表有两个功能按钮：一个是计数和停止计数按钮，当第一次按下此按钮时，秒表开始计数，再一次按下时，秒表停止计数，并显示所计的数字；另一个是清零按钮，当按下此按钮时，秒表清零。在数码管上采用动态扫描显示输出。-Stopwatch has two function buttons: one button count and stop counting when the first time you press this button, the stopwatch starts counting, wh
fpga_advantages
- FPGA advantages and disadvantages
Digital_Filter_Design
- 数字滤波器设计实例(Matlab\\VHDL)
fracn09
- Clock generation perl to vhdl oijoij
Manchester_Decoder_for_Wireless
- or1200 Manchester_Decoder_for_Wireless core code
example6
- 使用 key1 和 key2 来控制数据的加减，通过显示可以看出数据的变化。key1是控制数据加，key2 是控制数据减。可以从 0～9 显示。其中有按键消抖的方法-Key1 and key2 to control the use of the data increases or decreases can be seen by showing the data changes. key1 is to control the data increases, key2 is to control