资源列表
用VHDL实现秒表功能
- MEI SM
Project2_Template
- 用MATLAB下集成的XILINX模块判断是否是完美数-USE THE BLOCKS OF XILINX TO JUDGE A PERFECT NUMBER
Ali3329C_Bootloader
- bootloader for ali c
glVHDL
- 一个VHDL的小集合，把代码打开把其中的use work.butter_lib.all一句去掉就基本可以应用-A small collection of VHDL, the code open to the use work.butter_lib.all sentence can be applied to remove the basic
mylab
- 四选一数据选择器的VHDL语言编写源代码-Four data selectors choose a language VHDL source code
VCchuankou
- verilog ADPLL file with testbench
wb_conbus_latest.tar
- 源代码关于Verilog语言的wishbone总线-VHDL，verilog is very good
asynchro2bitupdownneg
- this a verilog code for asynchronous 2 bit up down counter with negative edge triggered.-this is a verilog code for asynchronous 2 bit up down counter with negative edge triggered.
VHDL
- 主要讲述了FPGA设计中的关键语言VHDL的学习-VHDL for FPGA study
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
mul
- 用VHDL语言实现十六位加法器（移位相加法）-VHDL language with Multiplier （Shift sum method）
fpga-fpdpsk
- FSK/PSK调制顶层文件 ，正弦波模块 ，正弦波模块初始化文件 ，振幅调整及波形选择模块 ，频率显示值地址产生模块 ，频率步进键核心模块 ，弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the freque